The present invention relates to a method of and a device for pulsed high-current loading of integrated circuits and structures.
One of the main causes of failure of integrated circuits are electrostatic discharges (ESD) during which the discharge current flows through the integrated circuit. Together with electric overstress (EOS), which is difficult to distinguished therefrom, they account for approximately 50% of the cases of field failure. External capacitors such as the human body or even the component as such (charged device) including the integrated circuit inside come into question as ESD charge sources. Charging is produced by friction (tribologic electricity) or by induction and contact in the electro-static field.
For protection of the integrated circuits protective structures are used on their inputs and outputs. These protective structures are intended, on the one hand, to take no influence on the functional integrity of the circuit, but, on the other hand, in the case of discharge they should branch off high currents along reliable paths around the core of the circuitry or out thereof, limiting the voltages to values which are not critical for the interior (e.g. gate oxides) of the circuit. For the synthesis of such a protective concept it is of vital importance to know the characteristics of these structures precisely within the pertinent current and time ranges.
Moreover, for the industrial product qualification the efficiency of such a protective concept must be verified and quantified in view of the electrostatic loads occurring in real operation. The qualification must be performed separately by housing types. To this end, characteristic load models such as the Human Body Model (HBM) and the Charged Device Model (CDM) with their derivatives have been defined. These models are substantially distinguished from each other by their current and time ranges. On account of the definition of a 1.5 k serial resistor and a 100 pF capacitor the Human Body Model presents a double exponential current development increasing within the range from up to 10 ns to approximately 0.66 A/kV precharging voltage and flowing via two terminals of the integrated circuit, By contrast, the capacitance of CDM discharge is defined only by the component as such or by its conductive elements relative to its environment. As the chip and housing area increases, this capacitance also increases due to the increasing number of pins ( greater than 300) and the reduction of the thickness of the housing. The risk of ESD commences when the terminals are separated after the chip has been pressed in the plastic housing, and still persists even after its assembly in a printed circuit board. As a result of ever-increasing automation, the probability of a load according to the Charged Device Model increases as well. The CDM model excels itself not only by the exchange of charges via an individual terminal of the circuit, but also by its very high currents of up to several Ampere, which are limited only by the terminal inductance and the sparking resistance and which are reached within fractions of a nano second.
Due to the high current, high voltage drops by several 10V may be established across the protective structures and supply lines, which become an imminent danger for the even thinner gate oxides, even when the protective structure responds at the sufficient rate. As the distance of the breakdown voltage from the gate oxides and pn junctions for protection and for more complex supply bus systems increases, the imminent risk continues rising which is involved by the extremely short high-intensity pulses of the CDM.
The quantification of the electrostatic load-bearing capacity is therefore realized in ESD testers in which the different loading models are implemented. Protective elements and integrated structures in the high-current range can be characterized by means of rectangular pulses which are, as a rule, generated by the discharge of lines and which are applied to the two terminals of a protective element.
The ESD load-bearing capability of integrated circuits in correspondence with the CDM model has so far been quantified in testers which are distinguished from each other by the type of the discharge contact, by the type of the device mounts, and by the charging principle. The standardization of the testing method has been and is strongly impeded by substantial correlation problems. One cause is the complex interactions among the integrated circuit, its housing, the test adapter and the testing device as such, which occur during the very short pulses. These interactions take an influence first on the discharge current and second on the effects which this current produces on the circuit. A key problem is the pulse measuring technique which is insufficient for the individual current increases ( less than 100 ps) of so steep a slope.
Among the known CDM testers a distinction is made among the following types:
(1) Non-Contact, Non-Socketed (NN)
The charged component is placed in a rear position on a grounded conductive support. For loading, a grounded low-inductance electrode is attached to the component terminal to be loaded. The discharge then takes place in dependence on the field intensity and the ignition conditions by sparks or metal contact. This technique, however, displays a bad reproducibility of the current development in the case of pre-charging voltages higher than 1 kV. Moreover, with vertically arranged (DIL), the contact is not reliable for very small or even bent terminals. Further uncertainties arise as a result of mechanical-electrical spring contacts. The mechanical positioning permits only a very slow test sequence. The insufficient bandwidth of the available pulse measuring technique creates additional problems. The sensitive HF cables and connectors, which are required for discharge current measurement, may prematurely age and falsify the test result in view of frequent re-positioning during the test.
(2) Contact, Non-Socketed (CN)
The charged component is placed in a rear position on a grounded conductive support. An opened relays connects the charged device to the ground of the tester. A relay is closed for loading.
In this method, however, only a decelerated low-amplitude discharge occurs as a consequence of the relay and its inductance. The method displays a bad reproducibility of the current development in the case of pre-charging voltages higher than 1 kV by spark discharge. Moreover, the contact is unreliable in the case of very small or even bent terminals. The mechanical positioning permits only a slow test sequence. The measuring technique of this method can be mapped on the technique of the xe2x80x9cnnxe2x80x9d type only conditionally.
(3) Non-Contact, Socketed (NS)
The component is arranged on a test mount, possibly a test adapter, or a printed circuit board to increase the spacings between the terminals. The test amount in its entirety, inclusive of all lines provided thereon, is charged relative to the testing system. For loading, one terminal is contacted by attaching two contacts under atmospheric conditions. The mount and board capacitance (background capacitance) present behind the component is discharged via this terminal. In this method a complex system of lines and line termination resistors determine the complex discharge current shape and, in combination with the integrated circuit, may result in unforeseeable effects. As significant pulse measuring methods are lacking, the result can only be transferred to other systems or to another type with difficulties or not all. Another disadvantage resides in the aspect that background capacitance taking an influence on the fail voltage and the physical failure signature increases the accumulated energy.
(4) Contact, Socketed (CS)
The component is disposed in a test mount, possibly a test adapter, or a printed circuit board to increase the spacings between the terminals. The test mount in its entirety, inclusive of all lines provided thereon, is charged relative to the testing system. For loading, one terminal is contacted via one or several relays, and the mount and board capacitance (background capacitance) present behind the component is discharged via this terminal. The disadvantages of this method correspond to those presented by the aforedescribed xe2x80x9cnsxe2x80x9d type.
In testing systems without a mount, a field-induced charging is also possible. In this operation the potential of the electrode under the device is raised for charging, and a first transient contact with the ground electrode is established. The potential of the electrode is then lowered again and the contact with the ground electrode is established a second time. During this cycle the device is normally loaded twice with alternating polarity.
Another known method relates to the xe2x80x9cSmall Capacitor Modelxe2x80x9d (SCM) which is currently used in Japan and where a charged 10 pF capacitor is contacted with the device terminal to be loaded. The reproducibility and transferability are strongly dependent on the actual structure in this case, too.
All the testing systems so far presented serve to load housed integrated circuits and modules exclusively. If they were employed directly for tests on the wafer level, the tip ought to be positioned with a precision of xc2x120 xcexcm. In real structures, the capacitance would be established substantially between the silicon substrate and the substrate support isolated therefrom, and the mobile charge would be located on the substrate underside of the integrated circuit. This, however is in opposition to the distribution of charges in housed devices which are located in correspondence with the unsocketed CDM techniques. Here the mobile charge is located on the metal coating on the chip surface and the metal parts of the housing.
The advantages and disadvantages of the test systems so far presented are complementary particularly in view of reproducibility and transferability of the load. A substantial improvement on the basis of the existing systems is not conceivable because in the predominantly pragmatic approaches oriented by the reproduction of field failure a physically unambiguous definition is missing which can be transferred from one system to the other.
A very fast rectangular-pulse generator, which is applied for characterizing integrated structures, is exhaustively discussed in the publication by H. Gieser, M. Haunschild: xe2x80x9cVery-Fast Transmission Line Pulsing of Integrated Structures and the Charges Device Modelxe2x80x9d, Proc. of the EOS/ESD Symposium, Phoenix, U.S.A., 1966, pages 85 et seq. In that device a rectangular-pulse generator is involved which operates on the transmission line principle and which generates pulses having a length between 3.5 ns and 11.5 ns, and which couples into an integrated structure via two terminals in correspondence with the time range reflectometric method (TDR) which is common in high-frequency technology.
As a result of a numerical superimposition of the flowing and returning voltage pulse the voltage and current load is determined on the analysed integrated structure.
The present invention is now based on the problem of providing a method of and a device for pulsed high-current loading, which permit the loading of complete integrated circuits with and without a housing, even at the wafer level, with ultra-short high-current pulses in a comparable and reproducible manner as well as the quantification of their load-bearing capacity in view of CDM-typical failure mechanisms.
The monitoring of the electrical failure criteria before and after loading should be possible without major structural modifications. Furthermore, this method is intended to increase the efficiency and the physically substantiated significance of the complete qualification process. It should moreover be possible to employ components and systems according to prior art, which are efficient in terms of costs and which are largelystandardized, instead of individual detail solutions, which are difficult to calibrate.
For the quantification of the electrostatic responsiveness and for the extraction of high-current parameters of integrated circuits and individual structures (DUTxe2x80x94Device under Test) a method and a device are proposed wherein a high current pulse can be injected via a terminal into the DUT under precisely defined marginal conditions. The substrate into which the circuit to be analysed is integrated, together with the reference electrode located at a defined distance, forms a capacitor which is dependent on the actual circuitry and determines the load parameters, with the dielectric of this capacitor being air as a rule.
The method of characterized by a intrinsic impedence (characteristic impedence) which is almost constant throughout the entire system and which is defined by the mechanical and the material properties. A complete semiconductor substrate wafer with a plurality of circuits may also be used as substrate.
Elements which generate pulses at a low stray dispersion (relays, solid-state switches) of a sufficient electric strength (e.g. 1 kV) and short response time (e.g. 300 ps) are expediently employed. Provisions may also be made for in situ measurement of the pulses approaching the device and reflected thereby. Furthermore, with a simple replacement of the capacitively coupled current injector by an injector having two terminals, or with the arrangement of a further contact electrode in a mount on the reference electrode, it is also possible to realize a current-voltage characterization of integrated structures up to the high-current range. With this technique and this device, failure mechanisms and pulse ranges of the electrostatic charging model xe2x80x9cCharged Device Model (CDM)xe2x80x9d are addressed where the load is determined in reality almost exclusively by the component as such or by the charge exchanged between the component and the environment within a few nano seconds.
The inventive device and the inventive method will be explained in more details by exemplary embodiments in the following, with reference to the drawing wherein: